1. Field of the Invention
The present invention relates to a clock generation circuit employed in a semiconductor memory device. More particularly, the present invention relates to a clock generation circuit generating an internal clock in synchronization with an external clock, and a semiconductor memory device including such a clock generation circuit.
2. Description of the Background Art
In a semiconductor device that operates in synchronization with an external clock such as an SDRAM (Synchronous Dynamic Random Access Memory), a clock generation circuit is provided in the semiconductor device. The internal circuit of the semiconductor device is generally controlled using an internal clock in synchronization with an external clock.
The circuit controlling the data input/output interface for the semiconductor device to send/receive data to/from an external source is under control using such an internal clock. Therefore, the data input/output timing is greatly influenced by the phase accuracy of the internal clock. The data output timing of an SDRAM will be described hereinafter as a typical example.
Referring to the timing chart of FIG. 22, a dock input circuit recognizes input of an external clock EXT.CLK at a timing (time t0) when the rising edge of external clock EXT.CLK exceeds the reference potential VREF. At time t1 corresponding to an elapse of tD1 from time t0, the clock input circuit renders internal clock CLKI active. This delay tD1 corresponds to the phase delay generated in the clock input circuit.
A data output operation is initiated with internal clock CLKI as a trigger. At time t2 corresponding to an elapse of tD2 from time t1, output data DOUT is provided. Therefore, access time tAC defined starting from the excess of external clock EXT.CLK over reference potential VREF up to excess of output data DOUT over a potential VTT which is the output terminate level is the sum of delay tD1 generated in the clock input circuit and delay tD2 generated in the data output operation. In a general SDRAM, the specification value of access time tAC is limited to 3 nsec-6 nsec. Delay time tD1 generated in the clock input terminal greatly affects access time tAC.
In accordance with the necessity of the semiconductor device operating at high frequency, the need arises to reduce the phase difference between the external clock edge and the input/output timing with respect to the semiconductor device. This is because the deviation in phase between the external clock edge and the data input/output timing is increased relatively with respect to the cycle of the external clock as the frequency of the external clock which is the reference in the operation of the semiconductor device becomes higher. The phase deviation will become too great to be neglected. In other words, the phase difference between the external clock edge and the operation timing of the input/output interface must be minimized in order to execute properly the command and data input/output with respect to the semiconductor device based on the external clock edge.
FIG. 23 is a timing chart of data output in a DDR-SDRAM (Double Data Rate-SDRAM).
Referring to FIG. 23, access time tAC corresponds to the period of time starting from time t0 corresponding to the crossing point of the potential levels of external clock EXT.CLK and an inverted clock EXT./CLK up to time t1 where output data DOUT exceeds the output terminate potential level VTT in a DDR-SDRAM.
In a DDR-SDRAM that inputs/outputs data in synchronization with both the rising and falling edges of an external clock, it is required that access time tAC takes a small value. The general specification of access time tAC is approximately xc2x10.75 nsec. In order to satisfy this access time specification, a clock generation circuit must be provided internally to control the phase difference between external clock EXT.CLK and internal clock CLKI, i.e. delay tD1 occurring at the time of internal clock generation according to external clock EXT.CLK. A DLL (Delay Locked Loop) generally formed of a variable delay circuit and a phase comparator or a PLL (Phase Locked Loop) is generally applied as such a clock generation circuit.
A structure of a clock generation circuit using a DLL employed in a conventional DDR-SDRAM will be described hereinafter.
FIG. 24 is a block diagram showing a structure of a conventional clock generation circuit employing a DLL.
Referring to FIG. 24, the clock generation circuit includes a clock input circuit 125, a variable delay circuit 130, replica circuits 140 and 160, a phase comparator 200, and a delay control circuit 150.
Clock input circuit 125 detects the crossing point of the potential levels of external clock EXT.CLK and inverted clock EXT./CLK forming complementary clocks to generate an internal clock CLK1. If the time required to generate internal clock CLK1 in clock input circuit 125 is tD1, internal clock CLK1 already lags in phase by delay tD1 from the crossing point of the potential levels of the complementary clocks at this stage.
Variable delay circuit 130 further delays internal clock CLK1 to generate an internal operation clock CLK2. Data output control circuit 50 operates in response to internal operation clock CLK2 to provide data DOUT to a data input/output terminal EXT.DQ.
Assuming that the cycle of external clock EXT.CLK is tCLK and the time required from activation of internal operation clock CLK2 up to the output of data DOUT is tD2, access time tAC can be set equal to external clock cycle tCLK by setting the delay time of variable delay circuit 130 to xe2x80x9ctCLKxe2x88x92(tD1+tD2)xe2x80x9d by delay control circuit 150. In this case, access time tAC is equivalently 0 as to the data output interface when viewed from outside the semiconductor device. Data output will be executed at a timing in synchronization with the external clock edge.
Since the delay value of variable delay circuit 130 is set to the foregoing xe2x80x9ctCLKxe2x88x92(tD1+tD2)xe2x80x9d, internal operation clock CLK2 is further delayed by two replica circuits 140 and 160 to be applied to phase comparator 200 as return clock RCLK. Replica circuit 140 functions to replicate the delay corresponding to delay amount tD2 generated at data output control circuit 50 with respect to internal operation clock CLK2. Similarly, replica circuit 160 replicates delay corresponding to delay amount tD1 generated at clock input circuit 125 with respect to the output of replica circuit 140.
Phase comparator 200 compares the phases between return clock RCLK output from replica circuit 160 and internal clock CLK1 of one succeeding cycle to generate a control signal UP/DOWN to increase/decrease the amount of delay of variable delay circuit 130 according to the phase difference.
Delay control circuit 150 generates a delay control signal CTRL according to control signals UP and DOWN to adjust the delay amount of variable delay circuit 130. When the phases of internal clock CLK1 and return clock RCLK match, delay control signal CTRL takes a certain fixed value, whereby the delay amount of variable delay circuit 130 is fixed. In this state, internal clock CLK1 is in phase with return clock RCLK. This state is called xe2x80x9clock statexe2x80x9d hereinafter.
Therefore, internal operation clock CLK2 is ahead in phase of internal clock CLK1 output from clock input terminal 125 by the delay amount applied at replica circuits 140 and 160. When the sum of the delay amount of replica circuits 140 and 160 exactly matches (tD2+tD1), the delay value of variable delay circuit 130 becomes xe2x80x9ctCLKxe2x88x92(tD1+tD2)xe2x80x9d, so that access time tAC seems to be 0, as mentioned before.
FIG. 25 is a block diagram showing another structure of a clock generation circuit employed in a DDR-SDRAM.
Referring to FIG. 25, the clock generation circuit generates internal operation clocks FCLK2 and BCLK2 corresponding to both the rising and falling edges of external clock EXT.CLK.
More specifically, the clock generation circuit includes a clock input circuit 125a responsive to a rising edge of external clock EXT.CLK to generate internal clock FCLK1, and a clock input circuit 125b responsive to a falling edge of external clock EXT.CLK to generate internal clock BCLK1.
Clock generation circuit 510 has the so-called dual delay line structure including variable delay circuits 130a and 130b corresponding to internal clocks FCLK1 and BCLK1, respectively.
Variable delay circuit 130a delays internal clock FCLK1 to generate an internal operation clock FCLK2, whereas variable delay circuit 130b delays internal clock BCLK1 to generate an internal operation clock BCLK2. Data output control circuit 50 responds to both internal operation clocks FCLK2 and BCLK2 to execute data output.
A DLL formed of variable delay circuit 130a, replica circuits 140 and 160, phase comparator 200 and delay control circuit 150, similar to the clock generation circuit shown in FIG. 24, is provided with respect to internal clock FCLK1. Synchronization can be established between the data output timing in response to internal operation clock FCLK2 and the rising edge of external clock EXT.CLK.
Since a delay amount identical to that of the variable delay circuit 130a is applied by variable delay circuit 130b also for internal clock BCLK1 generated in response to the falling edge of external clock EXT.CLK, internal operation clocks FCLK2 and BCLK2 can be rendered active alternately at a predetermined cycle.
As a result, data is output at the equivalent status of access time tAC=0 in synchronization with both the rising and falling edges of external clock EXT.CLK, when viewed from outside the semiconductor device.
Problems in the conventional clock generation circuit employing a DLL will be described based on a timing chart.
FIGS. 26A-26C are timing charts representing the operation of a conventional clock generation circuit shown in FIG. 24.
FIG. 26A corresponds to the case where data is output at the normal timing. Referring to FIG. 26A, internal clock CLK1 is rendered active at time t1 corresponding to an elapse of delay tD1 by the clock input circuit from time t0 where the potential levels of external clock EXT.CLK and inverted clock EXT./CLK become equal.
By the operation of the DLL, return clock RCLK is in phase with internal clock CLK1. Internal operation clock CLK2 is generated at a phase ahead of internal clock CLK1 by the delay time sum of tR2+tR1 by replica circuits 140 and 160. Output data Dout is output at time t0 delayed by tD2 from the activation timing of output trigger circuit CLK2.
Since the delay amounts set at replica circuits 160 and 140 are respectively equal to delay amount tD1 of clock input circuit 125 and delay amount tD2 of data output control circuit 150, access time tAC becomes 0 equivalently.
FIG. 26B corresponds to the case where the through rate of the rise and fall of external clock EXT.CLK and inverted clock EXT./CLK is small and the rising/falling time is great. Delay time tD1 generated at delay input circuit 125 is greater than that of FIG. 26A. Therefore, the actual delay time tD1 of clock input circuit 125 will become longer than delay time tR1 set at replica circuit 160, so that the output timing of output data DOUT is no longer in synchronization with external clock EXT.CLK. Therefore, the access time tAC will be generated at the plus side.
In contrast, when the through rate of the rise and fall of external clock EXT.CLK and inverted clock EXT./CLK is great and the rising/falling time is short as shown in FIG. 26C, the actual delay time tD1 of clock input circuit 125 will become shorter than delay time tR1set at replica circuit 160, opposite to that of FIG. 26B. As a result, external clock EXT.CLK is no longer in synchronization with the data output timing. Access time tAC will be generated at the minus side.
According to the structure of a conventional clock generation circuit that compensates for the delay generated at a clock input circuit by a replica circuit provided in the DLL, access tAC will vary according to the change in the through rate of the external clock.
Access time tAC also varies in response to the change in the potential levels at the crossing points of external clock EXT.CLK and inverted clock EXT./CLK. Furthermore, access time tAC varies when the actual amount of delay generated at the replica circuit and the clock input circuit differs from the predetermined designed value caused by variation in the waveform of the external clock as well as variation in the power supply voltage, power supply noise, temperature condition and the process. If access time tAC greatly varies by these factors, the specification of the data output timing cannot be satisfied. As a result, the semiconductor device cannot operate correctly.
An object of the present invention is to provide a clock generation circuit that can generate an internal clock of small variation in phase difference from an external clock, impervious to variation in the delay generated at a clock input circuit, and a semiconductor memory device including such a clock generation circuit.
According to an aspect of the present invention, a clock generation circuit supplying an operation clock in synchronization with an external clock to an internal circuit executing a predetermined operation includes a first clock input circuit, a first variable delay circuit, a first replica delay circuit, a first phase comparator, and a first delay control circuit. The first clock input circuit receives an external clock and an external reference clock which is a clock signal complementary to the external clock to generate a first internal clock. The first internal clock repeats transition between a first potential and a second potential according to potential level difference between the external clock and the external reference clock. The first variable delay circuit delays the first internal clock to generate a second internal clock supplied to the internal circuit as an operation clock. The first replica delay circuit further delays the second internal clock for a first predetermined time corresponding to the time required for a predetermined operation of the internal circuit to generate a third internal clock. The first phase comparator compares the phase where the potential levels of the external clock and the external reference clock cross with the phase of the third internal clock. The first delay control circuit controls a delay amount of the first variable delay circuit according to the phase comparison result of the first phase comparator.
According to another aspect of the present invention, a clock generation circuit supplying an operation clock in synchronization with an external clock to an internal circuit that carries out a predetermined operation includes a phase comparator, a delay control circuit, a control circuit, and a variable delay circuit. The phase comparator compares the phase where potential levels of the external clock and an external reference clock which is a clock signal complementary to the external clock cross with the phase of the operation clock. The delay control circuit generates a delay control signal according to the phase comparison result of the phase comparator. The control circuit generates an internal clock according to the operation clock. The variable delay circuit delays the internal clock according to the delay control signal to generate an operation clock.
According to a further aspect of the present invention, a semiconductor memory device operating in synchronization with an external clock includes a clock generation circuit. The clock generation circuit generates an operation clock to control the timing of the internal operation of the semiconductor memory device in synchronization with an external clock. The clock generation circuit includes a first clock input circuit receiving an external clock and an external reference clock which is a clock signal complementary to the external clock to generate a first internal clock. The first internal clock repeats a status transition according to the potential level of difference between the external clock and the external reference clock. The clock generation circuit further includes a variable delay circuit delaying the first internal clock to generate an operation clock, a replica delay circuit further delaying the operation clock for a predetermined time to generate a second internal clock, a phase comparator comparing the phase where potential levels of the external clock and the external reference clock cross with the phase of the second internal clock, and a delay control circuit controlling a delay amount of the variable delay circuit according to the phase comparison result of the phase comparator.
The main advantage of the present invention is that variation in the delay time caused in converting an external clock into an internal clock caused by variation in the external clock waveform, power supply voltage, power supply noise, temperature condition, process, and the like can be suppressed from adversely affecting the phase accuracy of the internal clock to maintain the phase accuracy of the internal clock favorably since the phase of the internal clock input to the phase comparator is directly compared with the phase where the potential levels of complementary external clocks cross.
In the case where an internal operation clock is generated using a PLL with complementary external clocks as the reference, variation in the delay time generated in the conversion of the external clock to the internal clock caused by variation in the external clock waveform, power supply voltage, power supply noise, temperature condition, process, and the like can be suppressed from adversely affecting the phase accuracy of the internal operation clock. Therefore, the phase accuracy of the internal operation clock can be maintained favorably.
Furthermore, the internal operation timing of the semiconductor memory device is controlled using an operation clock of small phase error generated by a clock generation circuit that directly compares the phase of the internal clock input to the phase comparator with the phase where potential levels of complementary external clocks cross. As a result, the semiconductor memory device can be operated properly at a predetermined timing in synchronization with complementary external clocks impervious to variation in the delay time generated when the external clock is converted into an internal clock.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.